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8-bit, 500 msps, 1.8 v analog-to-digital converter (adc) AD9286 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features single 1.8 v supply operation snr: 49.3 dbfs at 200 mhz input at 500 msps sfdr: 65 dbc at 200 mhz input at 500 msps low power: 315 mw at 500 msps on-chip interleaved clocking on-chip reference and track-and-hold 1.2 v p-p analog input range for each channel differential input with 500 mhz bandwidth lvds-compliant digital output on-chip voltage reference and sample-and-hold circuit dnl: 0.2 lsb serial port control options interleaved clock timing adjustment offset binary, gray code, or twos complement data format optional clock duty cycle stabilizer built-in selectable digital test pattern generation pin-programmable power-down function available in 48-lead lfcsp applications battery-powered instruments handheld scope meters low cost digital oscilloscopes ots: video over fiber general description the AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (adc) that supports interleaved operation and is optimized for low cost, low power, and ease of use. each adc operates at up to a 500 msps conversion rate with outstanding dynamic performance. the AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two adc cores (each running at one-half the clock frequency) to achieve the rated 500 msps. by using the spi, the user can accurately adjust the timing of the sampling edge per adc to minimize the image spur energy. the adc requires a single 1.8 v supply and an encode clock for full performance operation. no external reference components are required for many applications. the digital outputs are lvds compatible. the AD9286 is available in a pb-free, 48-lead lfcsp that is specified over the industrial temperature range of ?40c to +85c. product highlights 1. integrated 8-bit, 500 msps adc. 2. single 1.8 v supply operation with lvds outputs. 3. power-down option controlled via a pin-programmable setting. functional block diagram AD9286 clk? vin1+ vin1? vref vcm adc adc clock management clk+ a uxclk+ a uxclk? vin2? vin2+ 1.5 1.0v v ref ref select dco generation dco+ dco? rbias auxclken agnd avdd drvdd drgnd spi sdio/ pwdn oe sclk csb d7+ (msb), d7? (msb) d0+ (lsb), d0? (lsb) lvds output buffer output interleave 09338-001 figure 1.
AD9286 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications.......................................................................... 4 ? digital specifications ................................................................... 5 ? switching specifications .............................................................. 6 ? spi timing specifications ........................................................... 6 ? absolute maximum ratings............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution.................................................................................. 9 ? pin configuration and function descriptions........................... 10 ? typical performance characteristics ........................................... 12 ? equivalent circuits ......................................................................... 14 ? theory of operation ...................................................................... 15 ? adc architecture ...................................................................... 15 ? analog input considerations.................................................... 15 ? voltage reference ....................................................................... 15 ? rbias........................................................................................... 15 ? clock input considerations...................................................... 16 ? digital outputs ........................................................................... 18 ? built-in self-test (bist) and output test .................................. 19 ? built-in self-test (bist)............................................................ 19 ? output test modes..................................................................... 19 ? serial port interface (spi).............................................................. 20 ? configuration using the spi..................................................... 20 ? hardware interface..................................................................... 21 ? configuration without the spi ................................................ 21 ? spi accessible features.............................................................. 21 ? memory map .................................................................................. 22 ? reading the memory map register table............................... 22 ? memory map register table..................................................... 23 ? memory map register descriptions........................................ 25 ? applications information .............................................................. 26 ? design guidelines ...................................................................... 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 1/11revision 0: initial version
AD9286 rev. 0 | page 3 of 28 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, 1.0 v internal adc reference, unless otherwise noted. table 1. parameter 1 temperature min typ max unit resolution full 8 bits dc accuracy differential nonlinearity full 0.2 0.4 lsb integral nonlinearity full 0.1 0.3 lsb no missing codes full guaranteed offset error full 0 0.4 2.1 % fs gain error full 0 2 2.8 % fs matching characteristics offset error 2 full 0 0.4 2.1 % fs gain error full 0 0.05 0.2 % fs temperature drift offset error full 2 ppm/c gain error full 20 ppm/c analog input input span full 1.2 v p-p input common-mode voltage full 1.4 v input resistance (differential) full 16 k input capacitance (differential) full 250 ff full power bandwidth full 700 mhz voltage reference internal reference full 0.97 1 1.03 v input resistance full 3 k power supplies supply voltage avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v supply current i avdd full 125 130 ma i drvdd full 51 54 ma power consumption sine wave input 3 full 315 330 mw power-down power full 0.3 1.7 mw 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and an explanation of how these tests were completed. 2 see the interleave performance section. 3 measured with a low frequency, full-scale sine wave, with approximately 5 pf loading on each output bit.
AD9286 rev. 0 | page 4 of 28 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 1.0 v internal adc reference, vin = ?1.0 dbfs differential input, optimum timing value set, unless otherwise noted. table 2. parameter temperature min typ max unit signal-to-noise ratio (snr) f in = 10.3 mhz 25c 49.3 dbfs f in = 70 mhz 25c 49.3 dbfs f in = 96.6 mhz full 48.8 49.3 dbfs f in = 220 mhz 25c 49.3 dbfs signal-to-noise-and-distortion (sinad) f in = 10.3 mhz 25c 49.2 dbfs f in = 70 mhz 25c 49.2 dbfs f in = 96.6 mhz full 48.7 49.2 dbfs f in = 220 mhz 25c 49.2 dbfs effective number of bits (enob) f in = 10.3 mhz 25c 7.9 bits f in = 70 mhz 25c 7.9 bits f in = 96.6 mhz full 7.8 7.9 bits f in = 220 mhz 25c 7.9 bits worst second or third harmonic f in = 10.3 mhz 25c ?70 dbc f in = 70 mhz 25c ?70 dbc f in = 96.6 mhz full ?69 ?61 dbc f in = 220 mhz 25c ?65 dbc spurious-free dynamic range (sfdr) 1 f in = 10.3 mhz 25c 70 dbc f in = 70 mhz 25c 70 dbc f in = 96.6 mhz full 61 68 dbc f in = 220 mhz 25c 65 dbc worst other harmonic or spur f in = 10.3 mhz 25c ?71 dbc f in = 70 mhz 25c ?71 dbc f in = 96.6 mhz full ?71 ?64 dbc f in = 220 mhz 25c ?67 dbc crosstalk full ?80 dbc 1 excludes offset and alias spur (see the interleave performance section).
AD9286 rev. 0 | page 5 of 28 digital specifications avdd = 1.8 v, drvdd = 1.8 v, 1.0 v internal adc reference, ain = 5 mhz, full temperature, unless otherwise noted. table 3. parameter 1 temperature min typ max unit clock inputs (clk+, clk?, auxclk+, auxclk?) logic compliance lvds/pecl internal common-mode bias full 1.2 v differential input voltage 2 full 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 v high level input voltage full 1.2 3.6 v low level input voltage full 0 0.8 v high level input current full ?10 +10 a low level input current full ?10 +10 a input resistance (differential) 25c 20 k input capacitance 25c 4 pf l o g i c i n p u t s c s b high level input voltage full 1.2 drvdd + 0.3 v low level input voltage full 0 0.8 v high level input current full ? 5 ? 0.4 +5 a low level input current full ? 80 ? 63 ? 50 a input resistance 25c 30 k input capacitance 25c 2 pf sclk, sdio/pwdn, auxclken, oe high level input voltage full 1.2 drvdd + 0.3 v low level input voltage full 0 0.8 v high level input current full 50 57 70 a low level input current full ? 5 ? 0.4 +5 a input resistance 25c 30 k input capacitance 25c 2 pf digital outputs (d7+, d7? to d0+, d0?), lvds drvdd = 1.8 v differential output voltage (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) offset binary 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and an explanation of how these tests were completed. 2 specified for lvds and lvpecl only.
AD9286 rev. 0 | page 6 of 28 switching specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, ?1.0 dbfs differential input, 1.0 v internal reference, unless otherwise note d. table 4. parameter temperature min typ max unit clock input parameters input clock rate full 60 500 mhz clk period (t clk ) full 4 ns clk pulse width high (t ch ) full 2 ns data output parameters data propagation delay (t pd ) 1 3.7 ns dco propagation delay (t dco ) full 3.7 ns dco to data skew (t skew ) full ?280 ?60 100 ps pipeline delay (latency) full 11 cycles aperture delay (t a ) full 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 ps rms wake-up time 1 full 500 s out-of-range recovery time full 4 cycles 1 wake-up time is dependent on the value of the decoupling capacitors. spi timing specifications table 5. parameter description min typ max unit spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high sclk pulse width high 10 ns t low sclk pulse width low 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pi n to switch from an output to an input relative to the sclk rising edge 10 ns 09338-002 n ? 1 n ? 2 n + 1 m ? 11 n ? 11 m ? 10 n ? 10 m ? 9 n ? 9 m ? 8 m ? 7 n ? 8 n + 2 n + 4 n + 3 n t ch t clk m + 5 m + 4 m + 3 m + 1 m + 2 t a m m ? 1 v in1+, vin1? v in2+, vin2? clk+ clk? dco+, dco? data t a t dco t skew t pd timing diagrams figure output timing diagram sample mode interleaved (default)
AD9286 rev. 0 | page 7 of 28 0 9338-005 n ? 1 n + 1 n ? 11 m ? 10 n ? 10 m ? 9 n ? 9 m ? 8 m ? 7 n ? 8 n ? 7 n + 2 n + 4 n + 5 n + 3 m + 5 m + 4 m + 3 m + 1 m + 2 m n m ? 1 vin1+, vin1? vin2+, vin2? clk+ clk? dco+, dco? data t a t ch t clk t dco t skew t pd figure 3. output timing diagram, sample mode = simultaneous, auxclken = 0 09338-006 n ? 11 m ? 11 m ? 10 n ? 10 m ? 9 n ? 9 m ? 8 m ? 7 n ? 8 clk+ clk? dco+, dco? data auxclk+ auxclk? n ? 1 n + 1 n + 2 n + 4 n + 5 n + 3 m + 5 m + 4 m + 3 m + 1 m + 2 m n m ? 1 vin1+, vin1? vin2+, vin2? t a t ch t clk t dco t skew t pd figure 4. output timing diagram, sample mode = si multaneous, auxclken = 1, clk and auxclk in phase
AD9286 rev. 0 | page 8 of 28 09338-007 clk+ clk? dco+, dco? data auxclk+ auxclk? n ? 1 n ? 2 n + 1 n + 2 n + 4 n + 3 n vin1+, vin1? vin2+, vin2? t a m ? 1 m + 1 m + 5 m + 4 m + 3 m + 2 m t a t ch t clk t dco t skew t pd n ? 11 m ? 11 m ? 10 n ? 10 m ? 9 n ? 9 m ? 8 m ? 7 n ? 8 figure 5. output timing diagram, sample mode = simultaneous, auxclken = 1, clk and auxclk out of phase
AD9286 rev. 0 | page 9 of 28 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v d0+/d0? through d7+/d7? to drgnd ?0.3 v to drvdd + 0.3 v dco+, dco? to drgnd ?0.3 v to drvdd + 0.3 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v auxclk+, auxclk? to agnd ?0.3 v to avdd + 0.2 v vin1, vin2 to agnd ?0.3 v to avdd + 0.2 v sdio/pwdn to drgnd ?0.3 v to drvdd + 0.3 v csb to agnd ?0.3 v to drvdd + 0.3 v sclk to agnd ?0.3 v to drvdd + 0.3 v environmental storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja jc unit 48-lead lfcsp (cp-48-12) 30.4 2.9 c/w esd caution
AD9286 rev. 0 | page 10 of 28 pin configuration and fu nction descriptions 09338-003 13 14 15 16 17 18 19 20 21 22 23 24 d2? d2+ d3? d3+ dco? dco+ d4? d4+ d5? d5+ d6? d6+ 48 47 46 45 44 43 42 41 40 39 38 37 avdd vin2? vin2+ avdd avdd vref avdd vcm avdd vin1+ vin1? avdd 1 2 3 4 5 6 7 8 9 10 11 12 avdd avdd auxclk+ auxclk? rbias auxclken drgnd drvdd d0? (lsb) d0+ (lsb) d1? d1+ avdd clk+ clk? csb sdio/pwdn sclk oe drgnd drvdd d7+ (msb) d7? (msb) 35 avdd 36 34 33 32 31 30 29 28 27 26 25 AD9286 top view (not to scale) pin 1 indicator notes 1. the exposed paddle must be soldered to the pcb analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. figure 6. pin configuration table 8. pin function descriptions pin no. mnemonic type description adc power pins 1, 2, 35, 36, 37, 40, 42, 44, 45, 48 avdd supply analog power supply (1.8 v nominal). 8, 27 drvdd supply digital output driver supply (1.8 v nominal). 7, 28 drgnd ground digital output ground. 0 agnd ground analog ground. pin 0 is the expose d thermal pad on the bottom of the package. this is the only ground conne ction, and it must be soldered to the pcb analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. adc analog pins 39 vin1+ input differential analog input pin (+) for channel 1. 38 vin1? input differential analog input pin (?) for channel 1. 46 vin2+ input differential analog input pin (+) for channel 2. 47 vin2? input differential analog input pin (?) for channel 2. 43 vref input/output voltage reference input/output. 5 rbias input/output external reference bias resistor. connect 10 k from rbias to agnd. 41 vcm output common-mode level bi as output for analog inputs. 34 clk+ input adc clock inputtrue. 33 clk? input adc clock inputcomplement. 3 auxclk+ input auxiliary adc clock inputtrue. 4 auxclk? input auxiliary adc clock inputcomplement. digital inputs 6 auxclken input auxiliary clock input enable. 29 oe input digital enable (active low) to tristate output data pins. digital outputs 26 d7+ (msb) output output data 7true. 25 d7? (msb) output output data 7complement. 24 d6+ output output data 6true. 23 d6? output output data 6complement.
AD9286 rev. 0 | page 11 of 28 pin no. mnemonic type description 22 d5+ output output data 5true. 21 d5? output output data 5complement. 20 d4+ output output data 4true. 19 d4? output output data 4complement. 16 d3+ output output data 3true. 15 d3? output output data 3complement. 14 d2+ output output data 2true. 13 d2? output output data 2complement. 12 d1+ output output data 1true. 11 d1? output output data 1complement. 10 d0+ (lsb) output output data 0true. 9 d0? (lsb) output output data 0complement. 18 dco+ output data clock outputtrue. 17 dco? output data cloc k outputcomplement. spi control pins 30 sclk input spi serial clock. 31 sdio/pwdn input/output spi serial data i/o (sdio)/power-down input in external mode (pwdn). 32 csb input spi chip select (active low).
AD9286 rev. 0 | page 12 of 28 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = 500 msps, dcs enable, 1.2 v p-p differential input, vin = ?1.0 dbfs, 64k sample, t a = 25c, unless otherwise noted. 0 ?20 ?40 ?60 ?80 ?100 ?120 0 50 100 150 200 250 amplitude (dbfs) frequency (mhz) 500msps 4.3mhz @ ?1dbfs snr = 48.4db (49.4dbfs) enob = 7.7 sfdr = 70.0dbc second harmonic third harmonic 09338-107 figure 7. single-tone fft with f in = 4.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 50 100 150 200 250 amplitude (dbfs) frequency (mhz) 500msps 220.3mhz @ ?1dbfs snr = 48.2db (49.2dbfs) enob = 7.7 sfdr = 66.4dbc second harmonic third harmonic 09338-108 figure 8. single-tone fft with f in = 220.3 mhz 80 60 70 50 40 30 20 10 0 ?45 0?5 ?10?15?20?25?30?35?40 sfdr/snr (db) ain power (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) reference line 09338-109 figure 9. sfdr/snr vs. input amplitude (ain) with f in = 2.2 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 50 100 150 200 250 amplitude (dbfs) frequency (mhz) 500msps 96.6mhz @ ?1dbfs snr = 48.2db (49.2dbfs) enob = 7.7 sfdr = 68.4dbc second harmonic third harmonic 09338-110 figure 10. single-tone fft with f in = 96.6 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 50 100 150 200 250 amplitude (dbfs) frequency (mhz) 500msps 29.1mhz @ ?7dbfs 32.1mhz @ ?7dbfs sfdr = 70.3dbc (77.3dbfs) 09338-111 figure 11. two-tone fft with f in1 = 29.1 mhz and f in2 = 32.1 mhz 100 0 10 20 30 40 50 60 70 80 90 ?50 ?5?10?15?20?25?30?35?40?45 sfdr/imd3 (db) ain power (dbfs) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) imd3 (dbc) 09338-112 figure 12. two-tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 29.1 mhz and f in2 = 32.1 mhz
AD9286 rev. 0 | page 13 of 28 75 70 65 60 55 50 45 0 50 100 150 200 250 300 350 400 450 500 snrfs/sfdr (dbfs/dbc) input frequency (mhz) sfdr +85c sfdr ?40c sfdr +25c snrfs ?40c snrfs +25c snrfs +85c 09338-113 figure 13. snrfs/sfdr vs. input frequency (f in ) and temperature 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 100 150 200 250 300 350 400 450 500 supply current (a) total power (w) encode frequency (mhz) total power i_avdd i_dvdd 09338-114 figure 14. supply current and power vs. encode 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 0 32 64 96 128 160 192 224 256 dnl error (lsb) output code 09338-115 figure 15. dnl error with f in = 4.3 mhz 100 95 90 85 80 75 70 65 60 55 50 ?3?2?10123 alias spur (dbfs) coarse timing adjustment (bits) 09338-116 +85c ?40c +25c figure 16. alias spur vs. coarse timing adjustment and temperature 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 0 32 64 96 128 160 192 224 256 inl error (lsb) output code 09338-118 figure 17. inl error with f in = 4.3 mhz
AD9286 rev. 0 | page 14 of 28 equivalent circuits avdd 1.2v avdd clk+ avdd clk? 10k ? 10k? 09338-019 figure 18. clock inputs avdd v in+ buf avdd vin? buf buf avdd v cml ~1.4v 8k ? 8k ? 09338-020 figure 19. analog inputs (v cml = ~1.4 v) drvdd drvdd drvdd csb 350 ? 30k ? 09338-021 figure 20. csb drvdd drvdd 350 ? 30k ? 09338-022 sclk, oe, auxclken figure 21. sclk, oe , auxclken drvdd s di o ctrl 350? 09338-023 30k? figure 22. sdio drvdd d7? to d0? d7+ to d0+ v+ v? v? v+ 09338-024 figure 23. lvds output driver
AD9286 rev. 0 | page 15 of 28 theory of operation the AD9286 is a pipeline-type converter. the input buffers are differential, and both sets of inputs are internally biased. this allows the use of ac or dc input modes. a sample-and-hold amplifier is incorporated into the first stage of the multistage pipeline converter core. the output staging block aligns the data, carries out error correction for the pipeline stages, and feeds that data to the output interleave block and, finally, to the output buffers. all user-selected options are programmed through dedicated digital input pins or a serial port interface (spi). adc architecture each interleaving channel of the AD9286 consists of a differential input buffer followed by a sample-and-hold amplifier (sha). this sha is followed by a pipeline switched-capacitor adc. the quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. the pipelined archi- tecture permits the first stage to operate on a new input sample, whereas the remaining stages operate on preceding samples. each stage of the pipeline, exclud ing the last, consists of a low resolution flash adc connected to a switched-capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage consists of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended mode. the output staging block aligns the data, ca rries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. the outputs from both interleaving channels are time interleaved to achieve an effective 500 msps. analog input considerations the analog inputs of the AD9286 are differentially buffered. for best dynamic performance, the source impedances driving vin1+, vin1?, vin2+, and vin2? should be matched such that common-mode settling erro rs are symmetrical. because the AD9286 interleaves two adc cores, special attention should be given, during board layout, to the symmetry of the two analog paths. mismatch introduces un desired distortion. the analog inputs are optimized to provide superior wideband performance and must be driven differentially. snr and sinad performance degrades significantly if the analog inputs are driven with a single-ended signal. a wideband transformer, such as mini-circuits? adt1-1wt, can provide the differential analog inpu ts for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 v. differential input configurations optimum performance is achi eved when driving the AD9286 in a differential input configuration. for baseband applications, the ada4937-1 differential driver provides excellent performance and a flexible interface to the adc (see figure 24 ). the output common-mode voltage of the AD9286 is easily set to 1.4 v, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. ? + 200 ? 227.4 ? 61.9 ? ada4937-1 1.2v p-p 0.1f 200 ? 200 ? vin1 vin2 + ? + ? 4.7pf 33? 33? AD9286 vcm 09338-025 figure 24. differential input configuration using the ada4937-1 the AD9286 can also be driven passively with a differential transformer-coupled input (see figure 25 ). to bias the analog input, the vcm voltage can be co nnected to the center tap of the secondary winding of the transformer. 49.9 ? 1.2v p-p vin1 vin2 + ? + ? 4.7pf 0.1f 33? 33? AD9286 vcm 09338-026 figure 25. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. voltage reference an internal differential voltag e reference creates positive and negative reference voltages that define the 1.2 v p-p fixed span of the adc core. this internal voltage reference can be adjusted by means of spi control. it can also be driven externally with an off-chip stable reference. see the memory map register descriptions section for more details. rbias the AD9286 requires the user to place a 10 k resistor between the rbias pin and ground. this re sistor, which is used to set the master current reference of the adc core, should have a 1% tolerance.
AD9286 rev. 0 | page 16 of 28 clock input considerations for optimum performance, clock the AD9286 sample clock inputs, clk+ and clk? (and, optionally, auxclk+ and auxclk?), with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. clock input options the AD9286 has a very flexible clock input structure. the clock input can be an lvds, lvpecl, or sine wave signal. each con- figuration that is described in this section applies to both clk+ and clk? and auxclk+ and auxclk?, when necessary. figure 26 and figure 27 show two preferred methods for clocking the AD9286. a low jitter clock sour ce is converted from a single- ended signal to a differential signal using either an rf transformer or an rf balun. the back-to-ba ck schottky diodes across the transformer/balun secondary limi t clock excursions into the AD9286 to approximately 0.8 v p-p differential. this limit helps prevent the larg e voltage swings of the clock from feeding through to other portions of the AD9286, while preserving the fast rise and fall times of the signal that are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2822 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr cloc k input 09338-027 figure 26. transformer-coupled differential clock 0.1f 0.1f schottky diodes: hsm2822 1nf 1nf 50 ? clk? clk+ adc clock input 09338-028 figure 27. balun-coupled differential clock if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 28 . the ad9510/ ad9511 / ad9512 / ad9513/ ad9514 / ad9515 / ad9516/ ad9517 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50k ? 50k ? clk? clk+ adc ad951x pecl driver c lock input c lock input 09338-029 figure 28. differential pecl sample clock a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 29 . the ad9510 / ad9511/ ad9512 / ad9513 / ad9514/ ad9515 / ad9516/ ad9517 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? 50k ? clk? clk+ adc ad951x lvds driver c lock input c lock input 09338-030 figure 29. differential lvds sample clock clocking modes the AD9286 powers up as a single-channel converter with inter- leaving enabled. in this mode, a single high speed clock, driving clk+ and clk?, is divided down into two half-speed clocks running 180 out of phase with each other, each driving their respective adc core. by strapping the two analog inputs together externally, the AD9286 operates as a single 500 msps adc. because the high sample rate is achieved by interleaving two adc cores, mismatch between the cores, board layout, and clock timing can cause unwanted distortion. the AD9286 has been designed with two well-matched adc cores to minimize mismatch. to aid the user in removing timing errors, the AD9286 provides both fine and coarse timing adjustments, per channel, through spi. these features are available at register 0x37 (fine) and register 0x38 (coarse). the AD9286 supports a mode that allows the user to provide two separate half-speed clocks, bypassing the internal clock timing circuits and permitting external control of the clock timing relationship for each interleave channel. when the sample mode is set to simultaneous (a ddress 0x09, bit 3 = 0) and the auxclken pin is tied to drvdd, the AD9286 expects a second clock on its auxiliary clock input (auxclk+, auxclk?).
AD9286 rev. 0 | page 17 of 28 . 5 as gain , as a function of gain mismatch, is shown in figure 30 . in this mode, the AD9286 can also function as a dual 8-bit, 250 msps converter. this may be useful in applications where both a single 8-bit, 500 msps and a dual 8-bit, 250 msps converter are needed. the clock management block requires that clk and auxclk be either 0 or 180 , relative to each other. if this requirement is satisfied, the circuit correctly time aligns the data coming out of each adc core. 85 80 75 70 65 60 55 50 45 00 0.4 0.3 0.2 0.1 alias spur (dbc) gain mismatch (% fs) 09338-032 if the user desires to operate the AD9286 as a dual 8-bit, 250 msps converter and supply only a single clock, this is achieved by setting sample mode to simultaneous, with the auxclken pin tied to agnd. in this mode, the two adc cores sample simultaneously. for a summary of all supported clocking modes, see table 9 . the AD9286 supports the clocking of each internal adc with separate clocks. by setting auxclken to drvdd, the user can supply a differential auxiliary clock to auxclk+ and auxclk?. in this mode, each internal adc core has a maximum sample rate of 250 msps. this mode bypasses the internal timing adjustment blocks. figure 30. as gain as a function of gain mismatch the magnitude of the alias spur (as) contributed by a timing error is shown in equation 4. as timing (dbc) = 20 log( as timing ) = 20 log( ep /2) (4) where ep = a t e ( radians ), with a as the analog input frequency and t e as the clock skew error. interleave performance the AD9286 achieves 500 msps conversion by time interleaving two 250 msps adc channels. although this technique is sufficient in achieving 8-bit performance, quantifiable errors are introduced. these errors come from three sources: gain mismatch, imperfect out-of-phase sampling, and offset mismatch between the two channels. distortion appears spectrally in two distinct ways: gain and timing mismatch appear as an alias spur (see equation 1), and offset mismatch appears as a spur located at the nyquist rate of the converter (see equation 2). as timing , as a function of timing error, is shown in figure 31 . f alias_spur = f s /2 ? f in (1) where: f s is the interleaved sample rate. f in is the analog input frequency. f offset_spur = f s /2 (2) 85 80 75 70 65 60 55 50 45 01 10 8 6 4 2 alias spur (dbc) timing error (ps) 09338-033 2 where f s is the interleaved sample rate. figure 31. as timing as a function of timing error the magnitude of the alias spur (as) contributed by a gain error is shown in equation 3. the total magnitude of the alias spur (as) is shown in equation 5. as total (db) = 20 log(( as gain ) 2 + ( as timing ) 2 ) (5) as gain (dbc) = 20 log( as gain ) = 20 log( g e /2) (3) where: g e = gain_error_ratio = 1 ? v fs1 / v fs2 . v fsn is the full-scale voltage of core n . table 9. supported clocking modes effective umber of channels maximum c freuency auc freuency auc phase relative to c auce spi register address 0x09 bit 3 clock timing adjust one 500 msps n/a n/a low 1 internal two 250 msps n/a n/a low 0 n/a two 250 msps clk 0 high 0 n/a one 250 msps clk 180 high 0 external
AD9286 rev. 0 | page 18 of 28 . 5 the magnitude of the offset spur (os) is shown in equation 6. os offset (dbfs) = 20 log( offset 2/2 resolution ) (6) where: offset is the channel-to-channel offset in codes. resolution is the resolution of the converter (eight bits). os offset , as a function of offset mismatch, is shown in figure 32 . 60 55 50 45 40 35 30 25 20 02 2.0 1.5 1.0 0.5 offset spur (dbfs) offset mismatch (% fs) 09338-034 figure 32. os offset as a function of offset mismatch due to the orthogonal relationship between the gain and timing errors, it is impossible to correct for one with the other. to mini- mize channel-to-channel gain error, the AD9286 is designed to have very close gain matching between the two channels. address 0x37 and address 0x38 of the spi provide the ability to add delay to either clock path to realize a minimum clock skew error. also provided via the spi, in address 0x10, is the ability to minimize the channel-to-channel offset error. digital outputs digital output enable function ( oe ) the AD9286 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the oe pin. when oe is set to logic level high, the output drivers for both data buses are placed into a high impedance state.
AD9286 rev. 0 | page 19 of 28 built-in self-test (bist) and output test the AD9286 includes a built-in self -test feature that is designed to enable verification of the integrity of each channel, as well as facilitate board level debugging. a built-in self-test (bist) feature that verifies the integrity of the digital datapath of the AD9286 is included. various output test options are also provided to place predictable values on the outputs of the AD9286. built-in self-test (bist) the bist is a thorough test of the digital portion of the selected AD9286 signal path. perform the bist test after a reset to ensure that the part is in a known stat e. during bist, data from an internal pseudorandom noise (pn) source is driven through the digital datapath of both channels, starting at the adc block output. at the datapath output, crc logic calculates a signature from the data. the bist sequence runs for 512 cycles and then stops. when the test is completed, the bist compares the signature results with a predetermined value. if the signatures match, the bist sets bit 0 of register 0x0e, signifying that the test passed. if the bist test fails, bit 0 of register 0x0e is cleared. the outputs are connected during this test, so the pn sequence can be observed as it runs. writing a value of 0x05 to register 0x0e runs the bist. this enables the bit 0 (bist enable) of register 0x0e and resets the pn sequence generator, bit 2 (bist init) of register 0x0e. at the completion of the bist, bit 0 of register 0x0e is automatically cleared. the pn sequence can be continued from its last value by writing a 0 to bit 2 of regi ster 0x0e. however, if the pn sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. at that point, the user must rely on verifying the output data. output test modes the output test options are described in table 1 3 at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. some test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an-877 application note, interfacing to high speed adcs via spi .
AD9286 rev. 0 | page 20 of 28 serial port interface (spi) the AD9286 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are documented in the memory map section. for detailed operational information, see the an-877 application note, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: sclk, sdio, and csb (see table 10 ). sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. sdio (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 10. serial port interface pins pin function sclk serial clock. a serial shift clock input that is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. a dual-purpose pin that typically serves as an inp ut or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of csb, in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 33 . other modes involving csb are available. the csb pin can be held low indefinitely, which permanently enables the device; this is called streaming. csb can stall high between bytes to allow for additional external timing. when the csb pin is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. during the instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits, as shown in figure 33 . all data is composed of 8-bit words. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. this allows the serial data input/output (sdio) pin to change direction, from an input to an output, at the appropriate point in the serial frame. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, the serial data input/output (sdio) pin changes direction, from an input to an output, at the appropriate point in the serial frame. data can be sent in msb-first mode or in lsb-first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09338-004 figure 33. serial port interface timing diagram
AD9286 rev. 0 | page 21 of 28 hardware interface the pins described in table 10 constitute the physical interface between the programming device of the user and the serial port of the AD9286. the sclk and csb pins function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note, micro- controller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9286 to prevent these signals from transitioning at the converter inputs during critical sampling periods. sdio/pwdn serves a dual function when the spi interface is not being used. when the pin is strapped to avdd or ground during device power-on, it is associated with a specific function. the mode selection table (see table 11 ) describes the strappable functions that are supported on the AD9286. table 11. mode selection pin external voltage configuration avdd (default) chip in full power-down sdio/pwdn agnd normal operation avdd outputs in high impedance oe agnd (default) outputs enabled configuration without the spi in applications that do not interface to the spi control registers, the sdio/pwdn pin serves as a standalone, cmos-compatible control pin. when the device is powered up, it is assumed that the user intends to use the sdio, sclk, and csb pins as static control lines for the output enable and power-down feature control. in this mode, connecting the csb chip select to avdd disables the serial port interface. spi accessible features table 12 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an-877 application note, interfacing to high speed adcs via spi . the AD9286 part-specific features are described in detail in table 13 . table 12. features accessible using the spi feature description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay voltage reference allows the user to set the voltage reference
AD9286 rev. 0 | page 22 of 28 memory map reading the memory map register table each row in the memory map register table (see table 13 ) has eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02), the device index and transfer registers (address 0x05 and address 0xff), and the program registers (address 0x08 to address 0x38). table 13 documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for more information on this function and others, see the an-877 application note, interfacing to high speed adcs via spi. this document details the functions controlled by register 0x00 to register 0xff. open locations all address and bit locations that are not included in the spi map are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open. if the entire address location is open, it is omitted from the spi map (for example, address 0x13) and should not be written. default values after the AD9286 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table (see table 13 ). logic levels a n explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? bit is cleared is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x38 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. setting the transfer bit allows these registers to be updated internally and simultaneously. the internal update takes place when the transfer bit is set, and then the bit autoclears. channel-specific registers some channel setup functions can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in the memory map register table as local. these local registers and bits can be accessed by setting the appropriate channel 1 (bit 0) or channel 2 (bit 1) bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, set only channel 1 or channel 2 to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel 1. registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
AD9286 rev. 0 | page 23 of 28 memory map register table all address and bit locations that are not included in table 13 are not currently supported for this device. table 13. memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 nibbles are mirrored so that lsb- first or msb- first mode registers correctly, regardless of shift mode 0x01 chip id (global) 8-bit chip id 0x0a unique chip id used to differentiate devices; read only 0x02 chip grade (global) open speed grade id 100 = 500 msps open 0x40 unique speed grade id used to differentiate devices; read only device index and transfer registers 0x05 device index a open adc 2 default adc 1 default 0xff bits are set to determine which on- chip device receives the next write command; default is all devices on the chip 0xff transfer open transfer 0xff synchronous transfer of data from the master shift register to the slave program registers (may or may not be indexed by device index) 0x08 modes (global) open internal power-down mode 00: chip run 01: full power-down 10: reserved 11: reserved 0x00 determines various generic modes of chip operation 0x09 clock (global) open sample mode 0: simul- taneous 1: inter- leaved open clock boost duty cycle stabilizer 0x09 0x0d test mode (local) open reset pn23 gen reset pn9 gen open output test mode 000: off 001: midscale short 010: +fs short 011: ?fs short 100: checkerboard output 101: pn23 sequence 110: pn9 sequence 111: one-/zero-word toggle 0x00 when test mode is set, test data is placed on the output pins in place of normal data 0x0e bist (local) open bist init open bist enable 0x00 bist mode config
AD9286 rev. 0 | page 24 of 28 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0f adc input (global/local) open analog disconnect (local) common- mode input enable (global) open 0x00 0x10 offset (local) open offset adjust (twos complement format) 0111: +7 0110: +6 0001: +1 0000: 0 1111: ?1 1001: ?7 1000: ?8 0x00 device offset trim 0x14 output mode (local) open output enable open output invert data format select 00: offset binary 01: twos complement 10: gray code 11: reserved 0x00 configures the outputs and the format of the data 0x16 output phase (global) dco invert open 0x00 0x18 voltage reference (global) open voltage reference and input full-scale adjustment (see table 14 ) 0x00 selects/ adjusts v ref 0x24 misr lsb (local) lsbs of multiple input shift register (misr) 0x00 misr least significant byte; read only 0x25 misr msb (local) msbs of multiple input shift register (misr) 0x00 misr most significant byte; read only 0x37 open fine timing skew 0000: 0.0 ps 0001: 0.075 ps 1111: 1.125 ps 0x00 determines the clock delay that is introduced into the sampling path 0x38 timing adjust (local) open coarse timing skew 0000: 0.0 ps 0001: 1.2 ps 1111: 18 ps 0x00 determines the clock delay that is introduced into the sampling path
AD9286 rev. 0 | page 25 of 28 memory map register descriptions for more information about functions controlled in register 0x00 to register 0xff, see the an-877 application note, interfacing to high speed adcs via spi . voltage reference (register 0x18) bits[7:5]reserved bits[4:0]voltage reference bits[4:0] scale the internally generated voltage reference and, consequently, the full scale of the analog input. within this register, the reference driver can be configured to be more easily driven externally by reducing the capacitive loading. the relationship between the v ref voltage and the input full scale is described by equation 7. see table 14 for a complete list of register settings. input_full_scale = v ref 1.2 (7) table 14. v ref and input full scale (register 0x18) value v ref (v) full scale (v) 0x14 0.844 1.013 0x15 0.857 1.028 0x16 0.87 1.044 0x17 0.883 1.060 0x18 0.896 1.075 0x19 0.909 1.091 0x1a 0.922 1.106 0x1b 0.935 1.122 0x1c 0.948 1.138 0x1d 0.961 1.153 0x1e 0.974 1.169 0x1f 0.987 1.184 0x00 1 1.200 0x01 1.013 1.216 0x02 1.026 1.231 0x03 1.039 1.247 0x04 1.052 1.262 0x05 1.065 1.278 0x06 1.078 1.294 0x07 1.091 1.309 0x08 1.104 1.325 0x09 1.117 1.340 0x0a 1.13 1.356 0x0b 1.143 1.372 0x0c 1.156 1.387 0x0d 1.169 1.403 0x0e 1.182 1.418 0x0f 1.195 1.434 0x10 1.208 1.450 0x11 1.221 1.465 0x12 1.234 1.481 0x13 external external 1.2
AD9286 rev. 0 | page 26 of 28 applications information design guidelines before starting design and layout of the AD9286 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the AD9286, it is strongly recom- mended that two separate supplies be used. use one 1.8 v supply for analog (avdd); use a separate 1.8 v supply for the digital output supply (drvdd). if a common 1.8 v avdd and drvdd supply must be used, the avdd and drvdd domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. several different decoupling capacitors can be used to cover both high and low frequencies. locate these capacitors close to the point of entry at the printed circuit board (pcb) level and close to the pins of the part, with minimal trace length. a single pcb ground plane should be sufficient when using the AD9286. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat sink recommendations the exposed paddle (pin 0) is the only ground connection for the AD9286; therefore, it must be connected to analog ground (agnd) on the customer pcb. to achieve the best electrical and thermal performance, mate an exposed (no solder mask), continuous copper plane on the pcb to the AD9286 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug these vias with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. for detailed information about packaging and pcb layout of chip scale packages, see the an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. rbias the AD9286 requires that a 10 k resistor be placed between the rbias pin and ground. this resistor, which sets the master current reference of the adc core, should have at least a 1% tolerance. reference decoupling decouple the vref pin externally to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9286 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
AD9286 rev. 0 | page 27 of 28 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 4.25 4.10 sq 3.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 042809-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 34. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9286bcpz-500 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-12 AD9286bcpzrl7-500 ?40c to +85c 48-lead lead fr ame chip scale package [lfcsp_vq] cp-48-12 AD9286-500ebz evaluation board 1 z = rohs compliant part.
AD9286 rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09338-0-1/11(0)

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